a research team at the university of illinois has pioneered a novel silicon‑based circuit‑stacking process based on vertical integration, opening up an entirely new pathway to sustain moore’s law—when conventional planar scaling approaches physical limits, three-dimensional space emerges as a critical breakthrough for enhancing chip performance.
this technology departs from the conventional approach of continually shrinking transistor dimensions, instead achieving a dramatic increase in transistor density within a single chip by precisely stacking multiple ultra‑thin silicon nanofilms. it also significantly reduces interconnect distances, thereby markedly boosting computational density while lowering power consumption and latency.
at its core, the method innovatively employs a roller‑assisted lamination process to transfer atomically thin single‑crystal silicon nanofilms onto pre‑fabricated underlying circuits without damage, ensuring high‑precision alignment between layers and superior electrical characteristics. researchers note that this approach is highly compatible with existing cmos manufacturing lines, offering clear industrialization potential and holding promise for accelerating the deployment of high‑performance 3d processors and high‑bandwidth processing‑in‑memory chips.
